When the techniques of packet communication are extended beyond digital data communications to other types of information transfer, e.g., voice and image communication, the packet handling capacities required of the packet network elements must necessarily be increased manifold. One example of a high capacity packet network element is the fast packet switching system disclosed in U.S. Pat. No. 4,550,397, issued to J. S. Turner et al. on Oct. 29, 1985. In the Turner system, a high packet capacity is achieved in a self-routing network comprising multiple stages of switching nodes employing variable buffering techniques to decrease the packet delay across the network. An alternate routing mechanism is used to improve the network capacity under unbalanced traffic conditions that would otherwise cause a number of routes communicating a large amount of traffic to be channeled through one node. As a consequence of the alternate routing, packets are not necessarily received at their destination in the same order they were transmitted and, in many cases, some packet reordering mechanism must be implemented at the destination. Although the Turner et al. system represents an important advance in self-routing networks, the cumulative delay of packets through the multi-stage network and the reordering of packets required when alternate network routes are used to convey order-sensitive traffic, are significant problems in many applications.
A second known approach to the problem of switching packetized information is disclosed in U.S. Pat. No. 4,524,440, issued to M. Orsic. The Orsic system is referred to as a fast circuit switching system since a separate circuit is established for each packet-sized data communication. Information is conveyed from a number of communications modules in source channels to a number of port controllers and to a network. Information is conveyed from the network to destination channels. Each communications module includes a transmitter that transmits circuit setup request signals defining destination channels and also transmits data. Each port controller stores one of a number of status words defining the availability of the destination channels and each of these status words is cycled to each port controller. When one of the status words cycled to a port controller defines an available destination channel requested by a circuit setup request signal, the port controller transmits the circuit setup request signal and subsequent data to the network. The network responds to the circuit setup request signal by establishing a circuit to the requested destination channel. The port controllers of the Orsic system use the cycled status words to advantage to control the transmission of packets by the communications modules. However, the network in the Orsic system is relatively complex because it must respond to circuit setup request signals very quickly to establish the requested circuits to destination channels, and because it must distinguish between the request signals and the packets themselves since both are conveyed in the same channel.
In view of the foregoing, a recognized problem in the art is the difficulty in achieving a high-capacity packet switch without requiring large, complicated networks and complex packet processing techniques. Ancillary deficiencies of the prior art are the cumulative delay and the need for packet reordering as in a multi-stage self-routing packet network and the network complexity attendant with distinguishing between packets and request signals conveyed in the same channel and meeting stringent network requirements in establishing circuits rapidly in response to circuit setup request signals as in the Orsic system.